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1 HD66503 (240-channel common driver with internal lcd timing circuit) ade-207-301(z) '99.9 rev. 0.0 description the HD66503 is a common driver for liquid crystal dot-matrix graphic display systems. this device incorporates a 240 liquid crystal driver and an oscillator, and generates timing signals (alternating signals and frame synchronizing signals) required for the liquid crystal display. it also achieves low current consumption of 100 m a through the cmos process. combined with the hd66520, a 160-channel column driver with an internal ram, the HD66503 is optimal for use in displays for portable information tools. features lcd timing generator: 1/120, 1/240 duty cycle internal generator alternating signal waveform generator: pin programmable 2 to 63 line inversion recommended display duty cycle: 1/120, 1/240 (master mode): 1/120 to 1/240 (slave mode) number of lcd driver: 240 power supply voltage: 2.7 to 5.5v high voltage: 8 to 28-v lcd drive voltage low power consumption: 100 m a (during display) internal display off function oscillator circuit with standby function: 130 khz (max) display timing operation clock: 65 khz (max) (operating at 1/2 system clock) package: 272-pin tcp cmos process ordering information type no. tcp outer lead pitch ( m m) HD66503ta0 straight tcp 200 HD66503tb0 folding tcp 200
HD66503 2 pin arrangement 272 v2r 271 v5r 270 v6r 269 v1r 268 v eer 267 v cc2 266 m/s 265 doc 264 flm 263 cl1 262 m 261 reset 260 dispoff 259 duty 258 meor 257 mws0 256 mws1 255 mws2 254 mws3 253 mws4 252 mws5 251 shl 250 gnd 249 c 248 r 247 cr 246 v cc1 245 v eel 244 v1l 243 v6l 242 v5l 241 v2l x240 1 x239 2 x238 3 x237 4 x236 5 x235 6 x234 7 x233 8 x232 9 x231 10 x10 231 x9 232 x8 233 x7 234 x6 235 x5 236 x4 237 x3 238 x2 239 x1 240 top view note : this figure does not specify the tape carrier package dimensions.
HD66503 3 pin description classi- fication symbol pin no. pin name i/o number of pins functions power supply v cc1 , v cc2 246 267 v cc power supply 2v cc ?nd: logic power supply gnd 250 gnd power supply 1 v eel , v eer 245 268 v ee power supply 2v cc ? ee : lcd drive circuits power supply v1l, r v2l, r v5l, r v6l, r 244 269 241 272 242 271 243 270 v1 v2 v5 v6 input input input input 2 2 2 2 lcd drive level power supply see figure 1. control signals m/ s 266 master/slave input 1 controls the initiation and termination of the lcd timing generator. in addition, the input/output is determined of 4 signal pins: display data transfer clock (cl1); first line marker (flm); alternating signal (m); and display off control ( doc ). see table 1 for details. duty 259 duty input 1 selects the display duty cycle. low level: 1/120 display duty ratio high level: 1/240 display duty ratio mws0 to mws5 257 256 255 254 253 252 mws0 mws1 mws2 mws3 mws4 mws5 input 6 the number of line in the line alternating waveform is set during master mode. the number of lines can be set between 10 and 63. when using the external alternating signal or during slave mode, set the number of lines to 0. see table 2. meor 258 m exclusive- or input 1 during master mode, the signals alternating waveform output from pin m is selected. during low level, the line alternating waveform is output from pin m. during high level, pin m outputs an eor (exclusive or) waveform between a line alternating waveform and frame alternating waveform. set the pin to low during slave mode. see table 3.
HD66503 4 classi- fication symbol pin no. pin name i/o number of pins functions control signals cr, r, c 247 248 249 cr r c 3 these pins are used as shown in figure 4 in master mode, and as shown in figure 5 in slave mode. reset 261 reset input 1 the following initiation will be proceeded by setting to initiation. 1) stops the internal oscillator or the external oscillator clock input. 2) initializes the counters of the liquid crystal display timing generator and alternating signal (m) generator. 3) set display off control output ( doc ) to low and turns off display. after reset, display off control output ( doc ) will stay low for four more frame cycles (four clocks of flm signals) to prevent error display at initiation. the electrical characteristics are shown in table 4. see figure 2. however, when reset is performed during operation, ram data in the hd66520 which is used together with the HD66503 may be destroyed. therefore, write data to the ram again. lcd timing cl1 263 clock 1 i/o 1 the bidirectional shift register shifts data at the falling edge of cl1. during master mode, this pin-outputs a data transfer clock with a two times larger cycle than the internal oscillator (or the cycle of the external clock) with a duty of 50%. during slave mode, this pin inputs the external data transfer clock. flm 264 first line marker i/o 1 during master mode, pin flm outputs the first line marker. during slave mode, this pin inputs the external data first line marker. the shift direction of the first line marker is determined by duty and shl signal as follows. set signal duty to high during slave mode. see table 5. m 262 m i/o 1 pin m inputs and outputs the alternating signal of the lcd output.
HD66503 5 classi- fication symbol pin no. pin name i/o number of pins functions lcd timing shl 251 shift left input 1 pin shl switches the shift direction of the shift register. refer to flm for details. dispoff 260 display off input 1 turns off the lcd. during master mode, liquid crystal drive output x1 to x240 can be set to level v1 by setting the pin to low. by setting the hd66520 to level v1 in the same way, the data on the display can be erased. during slave mode, set dispoff high. doc 265 display off control i/o 1 controls the display-off function. during master mode, pin doc becomes an output pin and controls display off after reset and display off according to signal dispoff . in this case, connect this signal to the hd66520? pin dispoff . during slave mode, pin doc becomes an input pin for display off control signal. in this case, connect this signal to the master HD66503? pin doc . lcd drive output x1 to x240 240 to 1 x1 to x240 output 240 selects one from among four levels (v1, v2, v5, and v6) depending on the combination of m signal and display data. see figure 3. note: 30 input/outputs (excluding driver block)
HD66503 6 v1 v6 v5 v2 figure 1 lcd drive levels 2.7v v cc reset 0.8 v cc 0.2 v cc t reset t r figure 2 reset pin operation m signal display data output level 10 11 00 v2 v1 v6 v5 figure 3 lcd drive output
HD66503 7 table 1 m/ s signal status m/ s mode lcd timing generator cl1, flm, m, doc input/output state h master 1/120 or 1/240 duty cycle control output l slave stop input table 2 msw0 to msw5 signals status number of lines mws5 mws4 mws3 mws2 mws1 mws0 line alternating waveform pin m state 0000000 input 1000001 disable output 2000010 2-line alternation 3 to 63 0 to 1 0 to 1 0 to 1 0 to 1 1 to 1 1 to 1 3-line alternation to 63-line alternation table 3 meor signal status mode meor types of alternating waveforms output by pin m master h line alternating waveform ? frame alternating waveform l line alternating waveform slave l table 4 power supply conditions item symbol min typ max unit reset time t reset 1.0 m s rise time t r 200 ns table 5 flm status control mode duty shl shift direction of first line marker master h h x240 ? x1 l x1 ? x240 l h x120 ? x1, x240 ? x121 l x1 ? x120, x121 ? x240 slave h h x240 ? x1 l x1 ? x240
HD66503 8 internal block diagram lcd driver x1 to x240 v1l v6l v5l v2l level shifter bidirectional shift register d1 to d240 l1 to l240 v eel v cc1 v cc2 gnd v1r v6r v5r v2r v eer shl dispoff meor mws5 to mws0 duty m/s doc m flm cl1 r cr c m/s switcher lcd timing generator ac switching signal generator display off controller disps meors mws5s to mws0s mw0 docm crp mss cr oscillator level shifter reset dutys flmp cl1p shls docp mp flmm flm1 cl1m mm flmm cl1m 6 mls
HD66503 9 1. cr oscillator: the cr oscillator generates the HD66503 operation clock. during master mode, since the operation clock is needed, connect oscillation resistor r f with oscillation capacitor c f as follows. when the external clock is used, input external clock to pin cr and open pins c and r (figure 4). when using the HD66503 during slave mode, the operation clock will not be needed; therefore, connect pin cr to v cc and open pins c and r (figure 5). 2. liquid crystal timing generator: the liquid crystal timing generator creates various signals for the lcd. during master mode (m/ s = v cc ), the generator operates the HD66503? internal circuitry as a common internal driver using the generated lcd signals. in addition, signals cl1, m, and doc created by this generator can synchronously display data on a liquid crystal display by inputting them into the ram- provided segment driver hd66520 used together with HD66503. during slave mode (m/ s = gnd), this generator stops; the slave HD66503 operates based on signals cl1, m, doc , and flm generated by the master HD66503. 3. m/ s switcher: controls the input and output of lcd signals cl1, flm, m, and doc . this circuit outputs data when m/ s = v cc (master mode) and inputs data when m/ s = gnd (slave mode). 4. alternating signal generator: generates the alternating signal for the liquid crystal display. since the alternating signal decreases cross talk, it can alternate among 2 to 63 lines. the number of lines are specified with pins mws0 to mws5 is set to either v cc or gnd. moreover, the alternating signal can be externally input by grounding pins mws0 to mws5. in this case, the alternating signal is input from pin m. cr r f r c c open rcr external clock open c f figure 4 oscillator connection in master mode cr open r c open v cc figure 5 oscillator connection in slave mode
HD66503 10 5. display off control circuit: controls display-off function by using external display off signal disps and automatic display off signal flmm generated by the liquid crystal timing generator. automatic display off signal flmm is an internal signal that is used to turn off the display in four frames after signal reset is released. as a result, it is possible to turn off display using the display off signal that is sent randomly from an external lsi and automatically prevent incorrect display after reset release. 6. bidirectional shift register: this is a 240-bit bidirectional shift register. this register can change the shift direction using signal shl. during master mode, the scan signal of the common driver can be generated by sequentially shifting first line marker signal flm generated internally. during slave mode, a scan signal is generated by sequentially shifting first line marker signal flm input from pin flm. 7. level shifter: boosts the logic signal to a high voltage signal for the lcd. 8. lcd drive circuit: one of the lcd levels v1, v2, v5, and v6 are selected and output via pin x according to the combination of the data in the bidirectional shift register and signal m. table 6 output level of lcd circuit data in the shift register m output level 11v2 01v6 10v1 00v5
HD66503 11 internal function description 1. generation of signals cl1 and flm: signal cl1 shifts the scanning signal of the common driver. it is a 50% duty-ratio clock that changes level synchronously with the rising edge of oscillator clock cr. flm is a clock signal that is output once every 240 cl1 clock cycles for a duty of 1/240 (duty = v cc ), and every 120 cl1 clock cycles for a duty of 1/120 (duty = gnd). 2. generation of signal m: signal m alternates current in the lcd. it alternates the current to decrease cross talk after a certain number of lines ranging from 2 to 63 lines. the number of lines can be specified with pins mws0 to mws5 by setting each pin to either v cc or gnd (h or l). in addition, when pin meor is connected to gnd, signal m is a simple line alternating waveform, and when pin meor is connected to v cc , signal m is an eor (exclusive or) of line alternating waveform and frame alternating waveform. 12 240 (120) cr cl1 flm figure 6 generation of signals cl1 and flm (when mws0 to mws5 = 6) m (meor = gnd) m (meor = v cc ) 12345612 flm cl1 figure 7 generation of signal m
HD66503 12 3.auto display-off control: this functions prevents incorrect display after reset release. the display is turned off four frames following after reset release. in addition, the display off control signal shown in figure 8 is output by pin doc . this pin is connected to pin dispoff of the hd66520. 123456 reset flm doc figure 8 automatic display-off control function
HD66503 13 application example outline of HD66503 system configuration the HD66503 system configuration is outlined in figures 9 and 10. refer to the connection list (table 7) for connection details. when a single HD66503 is used to configure a small display (figure 9) when two HD66503s are used to configure a large display (figure 10) no. 1 lcd com1 to com240 hd66520 when using the internal oscillator refer to connection list a when using an external clock refer to connection list d no. 1 note: one HD66503 drives common signals and supplies timing signal to the hd66520. figure 9 when using a single HD66503 no. 1 lcd com1 to com240 hd66520 no. 2 upper display com241 to com480 lower display hd66520 when using the internal oscillator refer to connection list b when using an external clock refer to connection list e no. 1 refer to connection list c refer to connection list c no. 2 note: upper and lower displays are driven by separate HD66503s to ensure display quality. no. 1 operates in master mode, and no. 2 operates in slave mode. figure 10 when using two HD66503s
HD66503 14 HD66503 connection list table 7 HD66503 connection list mws0, mws1, connection mws2, mws3, example m/s duty mws4, mws5 meor reset dispoff cr r c cl1 flm m doc shl x1 to x240 a h h sets the number h from from r f r f to cl1 of to flm of to m of to dispoff l com1 to com240 of lines for cpu or controller hd66520 hd66520 hd66520 of hd66520 alternating the external current reset c f c f h com240 to com1 circuit b h h sets the number h from from r f r f to cl1 of to flm of to m of to doc of l com1 to com240 of lines for cpu or controller hd66520 hd66520 hd66520 HD66503 alternating the external HD66503 HD66503 HD66503 current reset c f c f t0 dispoff h com240 to com1 circuit of hd66520 c l h sets the number l from h h from cl1 from flm from m of from doc l com241 to com480 of lines for cpu or of HD66503 of HD66503 HD66503 of HD66503 alternating the external current reset h com480 to com241 circuit d h h sets the number h from from from to cl1 of to flm of to m of to dispoff l com1 to com240 of lines for cpu or controller external hd66520 hd66520 hd66520 of hd66520 alternating the external oscillator current reset h com240 to com1 circuit e h h sets the number h from from from to cl1 of to flm of to m of to doc of l com1 to com240 of lines for cpu or controller external hd66520 hd66520 hd66520 HD66503 alternating the external oscillator HD66503 HD66503 HD66503 current reset to dispoff h com240 to com1 circuit of hd66520 notes: h = v cc (fixed) l = gnd (fixed) ?means ?pen r f : oscillation resistor c f : oscillation capacitor
HD66503 15 example of system configuration (1) figure 11 shows a system configuration for a 240 160-dot lcd panel using segment driver hd66520 with internal bit-map ram. all required functions can be prepared for liquid crystal display with just two chips except for liquid crystal display power supply circuit functions. refer to timing chart (1) for details. x1 , x2, x3, ??? x240 shl dispoff duty m/s doc / 6 / 1 / 1 mws0 to 5 meor reset v cc cr v1, v2, v3, v4 rc lcd 240 160 seg1 seg2 seg159 seg160 com1 com2 line scan direction com239 com240 doc flm, cl1, m lcd driver lcd display timing control circuit HD66503 v1, v2, v5, v6 dispoff power supply circuit a0 to a15 db0 to db7 cs, we, oe 16 / 8 / 3 / 3 / 1 / hd66520 (id no. 0) ls0 ls1 shl 1 / figure 11 system configuration (1)
HD66503 16 example of system configuration (2) figure 12 shows a system configuration for a 240 320-dot lcd panel using segment driver hd66520 with internal bit-map ram. refer to timing chart (1) for details. x1, x2, x3, ??? x240 shl dispoff duty m/s doc / 6 / 1 / 1 mws0 to 5 meor reset v cc cr v1, v2, v3, v4 rc 320 seg161 seg162 seg319 seg320 com1 com2 line scan direction com239 com240 doc flm, cl1, m lcd driver lcd display timing control circuit HD66503 v1, v2, v5, v6 dispoff power supply circuit a0 to a15 db0 to db7 cs, we, oe 16 / 8 / 3 / 3 / 1 / hd66520 (id no. 2) lcd 240 seg1 seg2 seg159 seg160 hd66520 (id no. 0) ls0 ls1 shl v cc ls0 ls1 shl 1 / figure 12 system configuration (2)
HD66503 17 timing chart (1) 240 1 2 m cr cl1 10 11 12 20 21 22 120 121 122 130 131 132 140 141 142 240 1 2 flm v6 v2 v6 v5 v6 v1 v6 v5 v6 v5 v6 v5 v6 v5 v6 v5 v6 v2 v5 v6 v1 v5 v6 v5 v1 v6 v5 v6 v2 v5 v6 v5 v6 v5 v6 v5 v6 v5 v6 v1 v5 v1 10 lines 10 lines 10 lines 10 lines v1 v5 v5 x1 (com1) x2 (com2) x120 (com120) x121 (com121) x122 (com122) x240 (com240) figure 13 timing chart (1)
HD66503 18 example of system configuration (3) figure 14 shows a system configuration for a 320 480-dot lcd panel using segment driver hd66520 with internal bit-map ram. refer to timing chart (2) for details. x1, x2, x3, ??? x240 shl dispoff duty m/s doc / mws0 to 5 meor reset cr rc seg160 seg159 seg2 seg1 com1 com2 com239 com240 flm, cl1, m lcd driver HD66503 slave mode v1, v2, v5, v6 power supply circuit hd66520 (id no.0) lcd 480 seg320 seg319 seg162 seg161 hd66520 (id no.2) ls1 ls0 shl v cc ls0 ls1 shl seg1 seg2 seg159 seg160 com241 com242 seg161 seg162 seg319 seg320 hd66520 (id no.1) hd66520 (id no.3) ls0 ls1 shl v cc ls1 ls0 shl v cc x1, x2, x3, ??? x240 shl duty m/s doc cr r c lcd driver HD66503 master mode open open v cc dispoff reset mws0 to 5 meor flm, cl1, m com479 com480 320 v1, v2, v3, v4 320 / / / / / / / / 16 8 3 3 6 1 1 1 1 line scan cirection a0 to a15 db0 to db7 cs, we, oe figure 14 system configuration (3)
HD66503 19 timing chart (2) 480 1 2 m cr cl1 10 11 12 20 21 22 240 241 242 250 251 252 260 261 262 480 1 2 flm x1 (com1) x2 (com2) x240 (com240) v5 v6 v1 v6 v5 v6 v2 v5 v6 v5 v6 v1 10 lines 10 lines 10 lines 10 lines v6 v2 v6 v2 v5 v5 v1 HD66503 no. 1 x241 (com241) x242 (com242) x480 (com480) v5 v6 v1 v6 v5 v6 v2 v5 v6 v5 v6 v1 v6 v2 v6 v2 v5 v5 HD66503 no. 2 v1 v5 v1 v5 v1 v5 v6 v5 v1 v1 v6 v5 v1 v6 v6 v5 v1 figure 15 timing chart (2)
HD66503 20 power supply circuit v6l, v6r r1 v3l, v3r r1 v4l, v4r r2 v5l, v5r r1 r1 +3v v1l, v1r v cc1 , v cc2 v eel , v eer v2l, v2r ?5v 0v gnd contrast note: r1 4r1 + r2 1 15 = if r1 = 3 k w , then r2 = 33 k w the values of r1 and r2 vary with the lcd panel used. when the bias factor is 1/15, for example, the values of r1 and r2 can be determined as follows: figure 16 power supply circuit
HD66503 21 absolute maximum ratings item symbol ratings unit notes power voltage logic circuit v cc ?.3 to +7.0 v 2 lcd drive circuit v ee v cc ?30.0 to v cc + 0.3 v 5 input voltage (1) vt1 ?.3 to v cc + 0.3 v 2, 3 input voltage (2) vt2 v ee ?0.3 to v cc + 0.3 v 4, 5 operating temperature t opr ?0 to +75 c storage temperature t stg ?5 to +110 c notes: 1. if the lsi is used beyond its absolute maximum rating, it may be permanently damaged. it should always be used within the limits of its electrical characteristics in order to prevent malfunction or unreliability. 2. measured relative to gnd (0v). 3. applies to all input pins except for v1l, v1r, v2l, v2r, v5l, v5r, v6l, and v6r, and to input/output pins in high-impedance state. 4. applies to pins v1l, v1r, v2l, v2r, v5l, v5r, v6l, and v6r. 5. apply the same voltage to pairs v1l and v1r, v2l and v2r, v5l and v5r, v6l and v6r, and v eel and v eer . it is important to preserve the relationships v cc1 = v cc2 3 v1l = v1r 3 v6l = v6r 3 v5l = v5r 3 v2l = v2r 3 v eel = v eer
HD66503 22 electrical characteristics dc characteristics (v cc = 2.7 to 5.5v, v cc ? ee = 8 to 28v, gnd = 0v, ta = ?0 to +75 c) item symbol min typ max unit measurement condition notes input high level voltage vih 0.8 v cc ? cc v1 input low level voltage vil 0 0.2 v cc v1 output high level voltage voh v cc ?.4 v i oh = ?.4 ma 2 output low level voltage vol 0.4 v i ol = +0.4 ma 2 driver ?n resistance r on 2.0 k w v cc ? ee = 28v, load current: 150 m a 13, 14 input leakage current (1) i il1 ?.0 1.0 m a vin = 0 to v cc 1 input leakage current (2) i il2 ?5 25 m a vin = v ee to v cc 3 operating frequency (1) f opr1 10 200 khz master mode (external clock operation) 4 operating frequency (2) f opr2 5 500 khz slave mode 5 oscillation frequency (1) f osc1 70 100 130 khz c f = 100 pf 5%, r f = 51 k w 2% 6, 12 oscillation frequency (2) f osc2 21 30 39 khz c f = 100 pf 5%, r f = 180 k w 2% 6, 12 power consumption (1) i gnd1 80 m a master mode 1/240 duty cycle, c f = 100 pf, r f = 180 k w v cc ?nd = 3v, v cc ? ee = 28v 7, 8 power consumption (2) i gnd2 20 m a master mode 1/240 duty cycle external clock f opr1 = 30 khz v cc ?nd = 3v, v cc ? ee = 28v 7, 9 power consumption (3) i gnd3 10 m a slave mode 1/240 duty cycle during operation f cl = 15 khz v cc ?nd = 3v, v cc ? ee = 28v 7, 10
HD66503 23 item symbol min typ max unit measurement condition notes power consumption i ee 20 m a master mode 1/240 duty cycle, c f = 100 pf, r f = 180 k w v cc ?nd = 3v v cc ? ee = 28v, 7, 11 notes: 1. applies to input pins meor, mws0 to mws5, duty, shl, dispoff , m/ s , reset , and cr, and when inputting to input/output pins cl1, flm, doc , and m. 2. applies when outputting from input/output pins cl1, flm, doc , and m. 3. applies to v1l/r, v2l/r, v5l/r, and v6l/r. x1 to x240 are open. 4. figure 17 shows the external clock specifications: th 0.8v cc t rcp t fcp 0.5v cc 0.2v cc tl cr open rc external clock open min typ max unit 45 50 55 % 50 ns 50 ns duty t rcp t fcp th th + tl duty = 100% figure 17 external clock 5. regulates to operation frequency limits of the bidirectional shift register in the slavemode. 6. connect resistance rf and capacitance cf as follows: cr c f r f rc figure 18 timing components 7. input and output currents are excluded. when a cmos input is floating, excess current flows from the power supply through to the input circuit. to avoid this, vih and vil must be held to v cc and gnd levels, respectively. 8. this value is specified for the current flowing through gnd under the following conditions: internal oscillation circuit is used. each terminal of meor, mws0 to mws5, duty, shl, dispoff , m/ s , and reset is connected to v cc . oscillator is set as described in note 6. 9. this value is specified for the current flowing through gnd under the following conditions: each terminal of meor, mws0 to mws5, duty, shl, dispoff , m/ s , and reset is connected to v cc . oscillator is set as described in note 4.
HD66503 24 10. this value is specified for the current flowing through gnd under the following conditions: each terminal of meor, mws0 to mws5, duty, shl, doc , dispoff , reset , and cr is connected to v cc , m/ s to gnd, and frequency of cl1, flm, m is respectively established as follows. f cl1 = 15 khz, f flm = 62.5 hz, f m = 120 hz 11. this value is specified for the current flowing through v ee under the following condition described in note 8. do not connect any lines to pin x. 12. figure 19 shows a typical relation among ocsillation frequency r f and c f . oscillation frequency may vary with mounting conditions. 0 100 200 0 100 200 300 r f (k w ) f osc = (khz) c f = 100 (pf) figure 19 ocsillation frequency characteristics 13. indicates the resistance between one pin from x1 to x240 and another pin from the v pins v1l/r, v2l/r, v5l/r, and v6l/r, when a load current is applied to the x pin; defined under the following conditions: v cc ? ee = 28 (v) v1l/r, v6l/r = v cc ?/10 (v cc ? ee ) v5l/r, v2l/r = v ee + 1/10 (v cc ? ee ) v1l, v1r v6l, v6r v5l, v5r v2l, v2r connect any of these mos switch ron pin x (x1 to x240) figure 20 on resistance conditions
HD66503 25 14. v1l/r and v6l/r should be near the v cc level, and v5l/r and v2l/r should be near the v ee level. all these voltage pairs should be separated by less than d v, which is the range within which r on , the lcd drive circuits?output impedance is stable. note that d v depend on power supply voltages v cc ? ee . see figure 21. v v v cc v1l/r v6l/r v5l/r v2l/r v ee 6.4 2.5 828 v (v) v cc ? ee (v) figure 21 relationship between driver output waveform
HD66503 26 ac characteristics (v cc = 2.7 to 5.5v, v cc ? ee = 8 to 28v, gnd = 0v, ta = ?0 to +75 c) slave mode (m/ s = gnd) item symbol min typ max unit notes cl1 high-level width t cwh 500 ns 1 cl1 low-level width t cwl 500 ns 1 flm setup time t fs 100 ns 1 flm hold time t fh 100 ns 1 cl1 rise time t r 50ns1 cl1 fall time t f 50ns1 note: 1. based on the load circuit shown in figure 22. 30 pf (including jig capacitance) test point figure 22 load circuit 0.8 v cc t fs t cwh 0.2 v cc t r t f t fh 0.8 v cc 0.2 v cc t cwl cl1 flm figure 23 slave mode timing
HD66503 27 master mode (m/ s = v cc ) item symbol min typ max unit notes cl1 delay time t dcl1 1 m s flm delay time t dflm 1 m s m delay time t dm 500 ns flm setup time t fs t osc /2 ?500 ns 0.8 v cc t dcl1 t fs 0.2 v cc t dcl1 0.8 v cc 0.2 v cc t dflm 0.8 v cc 0.2 v cc 0.8 v cc 0.2 v cc t dflm t osc cr cl1 flm m t dm figure 24 master mode timing
HD66503 28 cautions 1. hitachi neither warrants nor grants licenses of any rights of hitachi? or any third party? patent, copyright, trademark, or other intellectual property rights for information contained in this document. hitachi bears no responsibility for problems that may arise with third party? rights, including intellectual property rights, in connection with use of the information contained in this document. 2. products and product specifications may be subject to change without notice. confirm that you have received the latest product standards or specifications before final design, purchase or use. 3. hitachi makes every attempt to ensure that its products are of high quality and reliability. however, contact hitachi? sales office before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support. 4. design your application so that the product is used within the ranges guaranteed by hitachi particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. hitachi bears no responsibility for failure or damage when used beyond the guaranteed ranges. even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail- safes, so that the equipment incorporating hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the hitachi product. 5. this product is not designed to be radiation resistant. 6. no one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from hitachi. 7. contact hitachi? sales office for any questions regarding this document or hitachi semiconductor products. hitachi, ltd. semiconductor & integrated circuits. nippon bldg., 2-6-2, ohte-machi, chiyoda-ku, tokyo 100-0004, japan tel: tokyo (03) 3270-2111 fax: (03) 3270-5109 copyright ?hitachi, ltd., 1998. all rights reserved. printed in japan. hitachi asia pte. ltd. 16 collyer quay #20-00 hitachi tower singapore 049318 tel: 535-2100 fax: 535-1533 url northamerica : http:semiconductor.hitachi.com/ europe : http://www.hitachi-eu.com/hel/ecg asia (singapore) : http://www.has.hitachi.com.sg/grp3/sicd/index.htm asia (taiwan) : http://www.hitachi.com.tw/e/product/sicd_frame.htm asia (hongkong) : http://www.hitachi.com.hk/eng/bo/grp3/index.htm japan : http://www.hitachi.co.jp/sicd/indx.htm hitachi asia ltd. taipei branch office 3f, hung kuo building. no.167, tun-hwa north road, taipei (105) tel: <886> (2) 2718-3666 fax: <886> (2) 2718-8180 hitachi asia (hong kong) ltd. group iii (electronic components) 7/f., north tower, world finance centre, harbour city, canton road, tsim sha tsui, kowloon, hong kong tel: <852> (2) 735 9218 fax: <852> (2) 730 0281 telex: 40815 hitec hx hitachi europe ltd. electronic components group. whitebrook park lower cookham road maidenhead berkshire sl6 8ya, united kingdom tel: <44> (1628) 585000 fax: <44> (1628) 778322 hitachi europe gmbh electronic components group dornacher stra? 3 d-85622 feldkirchen, munich germany tel: <49> (89) 9 9180-0 fax: <49> (89) 9 29 30 00 hitachi semiconductor (america) inc. 179 east tasman drive, san jose,ca 95134 tel: <1> (408) 433-1990 fax: <1>(408) 433-0223 for further information write to:

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